logic-level simulation
常见例句
- This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。 - With appropriate tool support, designers could perform execution or simulation and debugging on high-level system models to validate and verify system logic early on.
有了适当的工具支持，设计人员可以在高层的系统模型上进行执行或模拟，并调试，从而在早期确认并验证系统逻辑。 返回 logic-level simulation