CPPLL

常见例句

• And finally, a clock generator based on the 3rd order CPPLL is fully designed with UMC 0.25 CMOS process.
  最后，采用UMC 0.;25 CMOS工艺技术设计了一个用作时钟产生的三阶电荷泵锁相环。
• The application of my CPPLL is deserializer in video system, sampling high frequency data by low frequency clock to generate parallel low frequency data output.
  通过对时钟的频率和相位的同步，多相位输出，来对高速串行数据进行解串，输出低速并行信号。
• 4th order CPPLL
  4阶电荷泵锁相环
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